00001 #include "pic_rf_24l01.h"
00002 #include "pic_serial.h"
00003 #include <stdlib.h>
00004
00005 uns8 pic_rf_receive(uns8 *data, uns8 bytes_to_receive) {
00006
00007 uns8 fifo_status;
00008 uns8 res;
00009
00010 res = 0;
00011
00012
00013
00014
00015 pic_rf_read_register_inline(RF_RD_REG_FIFO_STATUS, &fifo_status, 1);
00016 while (!test_bit(fifo_status, 0)) {
00017
00018 pic_rf_read_register_inline(RF_R_RX_PAYLOAD, data, bytes_to_receive);
00019 pic_rf_send_command_inline(RF_WR_REG_STATUS, "\x40", 1);
00020 res++;
00021 pic_rf_read_register_inline(RF_RD_REG_FIFO_STATUS, &fifo_status, 1);
00022 }
00023
00024
00025
00026 return res;
00027 }
00028
00029
00030 uns8 pic_rf_send_command(uns8 cmd, uns8 *data, uns8 data_len) {
00031
00032 uns8 byte_counter, status;
00033
00034 clear_pin(rf_csn_port, rf_csn_pin);
00035 status = pic_rf_send_byte(cmd);
00036 for(byte_counter = 0 ; byte_counter < data_len ; byte_counter++) {
00037 pic_rf_send_byte(data[byte_counter]);
00038 }
00039
00040 set_pin(rf_csn_port, rf_csn_pin);
00041 return status;
00042 }
00043
00044 uns8 pic_rf_send_command_single(uns8 cmd, uns8 data) {
00045
00046 uns8 byte_counter, status;
00047
00048 clear_pin(rf_csn_port, rf_csn_pin);
00049 status = pic_rf_send_byte(cmd);
00050 pic_rf_send_byte(data);
00051 set_pin(rf_csn_port, rf_csn_pin);
00052 return status;
00053 }
00054
00055
00056 uns8 pic_rf_read_register(uns8 cmd, uns8 *data, uns8 data_len) {
00057
00058 uns8 byte_counter, status;
00059
00060 clear_pin(rf_csn_port, rf_csn_pin);
00061 status = pic_rf_send_byte(cmd);
00062 for(byte_counter = 0 ; byte_counter < data_len ; byte_counter++) {
00063 data[byte_counter] = pic_rf_send_byte(0);
00064 }
00065
00066 set_pin(rf_csn_port, rf_csn_pin);
00067 return status;
00068 }
00069
00070 uns8 pic_rf_read_register_int(uns8 cmd, uns8 *data, uns8 data_len) {
00071
00072 uns8 byte_counter, status;
00073
00074 clear_pin(rf_csn_port, rf_csn_pin);
00075 status = pic_rf_send_byte_int(cmd);
00076 for(byte_counter = 0 ; byte_counter < data_len ; byte_counter++) {
00077 data[byte_counter] = pic_rf_send_byte_int(0);
00078 }
00079
00080 set_pin(rf_csn_port, rf_csn_pin);
00081 return status;
00082 }
00083
00084
00085
00086
00087 uns8 pic_rf_send_byte(uns8 b)
00088 {
00089 uns8 bit_counter, status;
00090
00091 for(bit_counter = 0 ; bit_counter < 8 ; bit_counter++) {
00092 change_pin(rf_mosi_port, rf_mosi_pin, b.7);
00093 set_pin(rf_sck_port, rf_sck_pin);
00094 status <<= 1;
00095 status.0 = test_pin(rf_miso_port, rf_miso_pin);
00096 clear_pin(rf_sck_port, rf_sck_pin);
00097
00098 b <<= 1;
00099 }
00100 return status;
00101 }
00102
00103
00104 uns8 pic_rf_send_byte_int(uns8 b)
00105 {
00106 uns8 bit_counter, status;
00107
00108 for(bit_counter = 0 ; bit_counter < 8 ; bit_counter++) {
00109 change_pin(rf_mosi_port, rf_mosi_pin, b.7);
00110 set_pin(rf_sck_port, rf_sck_pin);
00111 status <<= 1;
00112 status.0 = test_pin(rf_miso_port, rf_miso_pin);
00113 clear_pin(rf_sck_port, rf_sck_pin);
00114
00115 b <<= 1;
00116 }
00117 return status;
00118 }
00119
00120
00121 void pic_rf_quick_init(char *my_config, uns8 my_channel, bit my_receive_on) {
00122
00123
00124 }
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00216
00217 void pic_rf_init(rf_config *my_config)
00218 {
00219 uns8 temp;
00220 uns8 options;
00221 uns8 data[5];
00222
00223 start_crit_sec();
00224
00225 clear_pin(rf_ce_port, rf_ce_pin);
00226 delay_ms(100);
00227
00228 temp = pic_rf_send_command(RF_WR_REG_CONFIG_REG,
00229 "\x3c", 1);
00230
00231
00232
00233 pic_rf_send_command(RF_WR_REG_SETUP_RETR,
00234 "\x00", 1);
00235
00236
00237 pic_rf_send_command(RF_WR_REG_SETUP_AW,
00238 "\x01", 1);
00239
00240
00241 pic_rf_send_command(RF_WR_REG_RF_SETUP,
00242 "\x07", 1);
00243
00244 pic_rf_send_command (RF_WR_REG_RF_CH,
00245 "\x02", 1);
00246
00247 data[0] = 0b11100111;
00248 data[1] = 0b11100111;
00249 data[2] = 0b11100111;
00250 pic_rf_send_command(RF_WR_REG_TX_ADDR,
00251 &data, 3);
00252
00253
00254 pic_rf_send_command(RF_WR_REG_RX_ADDR_P0,
00255 &data, 3);
00256
00257 pic_rf_send_command(RF_WR_REG_EN_AA,
00258 "\x00", 1);
00259
00260
00261
00262
00263 pic_rf_send_command(RF_WR_REG_RX_PW_P0,
00264 "\x15", 1);
00265
00266 pic_rf_send_command(RF_WR_REG_CONFIG_REG,
00267 "\x3f", 1);
00268
00269
00270 delay_ms(2);
00271 pic_rf_send_command (RF_FLUSH_TX,
00272 0, 0 );
00273 pic_rf_send_command (RF_FLUSH_RX,
00274 0, 0 );
00275
00276 pic_rf_send_command_inline(RF_WR_REG_STATUS, "\x40", 1);
00277 delay_ms(2);
00278
00279 set_pin(rf_ce_port, rf_ce_pin);
00280
00281 end_crit_sec();
00282 serial_print_str("got=");
00283 serial_print_int_hex(temp);
00284 serial_print_str(" ");
00285
00286 rf_current_mode_receive = 1;
00287 }
00288
00289
00290 void pic_rf_transmit(uns8 *data, uns8 bytes_to_transmit) {
00291
00292 uns8 byte_count, bit_count, temp, cd;
00293 start_crit_sec();
00294
00295 pic_rf_set_mode(TRANSMIT_MODE);
00296
00297
00298 pic_rf_read_register_inline(RF_RD_REG_CD, &cd, 1);
00299 serial_print_str("\n cd=");
00300 serial_print_int(cd);
00301 serial_print_nl();
00302 pic_rf_send_command(RF_W_TX_PAYLOAD, data, bytes_to_transmit);
00303
00304 set_pin(rf_ce_port, rf_ce_pin);
00305 delay_us(10);
00306 clear_pin(rf_ce_port, rf_ce_pin);
00307 delay_us(130);
00308 pic_rf_set_mode(RECEIVE_MODE);
00309
00310 end_crit_sec();
00311 }
00312 inline void pic_rf_receive_inline(uns8 *data, uns8 bytes_to_receive) {
00313 pic_rf_read_register_inline(RF_R_RX_PAYLOAD, data, bytes_to_receive);
00314 }
00315
00316 void pic_rf_receive2(uns8 *data, uns8 bytes_to_receive) {
00317
00318 pic_rf_receive_inline(data, bytes_to_receive);
00319 }
00320
00321
00322 void pic_rf_set_mode(uns8 requested_mode)
00323 {
00324 uns8 config_reg;
00325
00326 start_crit_sec();
00327
00328 if ((requested_mode == TRANSMIT_MODE) && (rf_current_mode_receive)) {
00329
00330
00331 clear_pin(rf_ce_port, rf_ce_pin);
00332 pic_rf_read_register(RF_RD_REG_CONFIG_REG, &config_reg, 1);
00333 clear_bit(config_reg, CONFIG_PRIM_RX);
00334 pic_rf_send_command(RF_WR_REG_CONFIG_REG, &config_reg, 1);
00335 rf_current_mode_receive = 0;
00336 } else if ((requested_mode == RECEIVE_MODE) && (!rf_current_mode_receive)) {
00337
00338
00339 pic_rf_read_register(RF_RD_REG_CONFIG_REG, &config_reg, 1);
00340 set_bit(config_reg, CONFIG_PRIM_RX);
00341 pic_rf_send_command(RF_WR_REG_CONFIG_REG, &config_reg, 1);
00342 set_pin(rf_ce_port, rf_ce_pin);
00343 rf_current_mode_receive = 1;
00344 }
00345
00346 end_crit_sec();
00347 }
00348
00349 void pic_rf_set_channel(uns8 channel)
00350 {
00351 start_crit_sec();
00352
00353 clear_pin(rf_ce_port, rf_ce_pin);
00354 pic_rf_send_command (RF_WR_REG_RF_CH,
00355 &channel, 1);
00356 if (rf_current_mode_receive) {
00357 set_pin(rf_ce_port, rf_ce_pin);
00358 }
00359 rf_current_channel = channel;
00360
00361 end_crit_sec();
00362 }
00363
00364 void pic_rf_setup() {
00365
00366 make_output(rf_ce_port, rf_ce_pin);
00367 make_output(rf_csn_port, rf_csn_pin);
00368 make_output(rf_sck_port, rf_sck_pin);
00369 make_output(rf_mosi_port, rf_mosi_pin);
00370 make_input (rf_miso_port, rf_miso_pin);
00371 make_input (rf_irq_port, rf_irq_pin);
00372
00373 set_pin(rf_csn_port, rf_csn_pin);
00374 clear_pin(rf_ce_port, rf_ce_pin);
00375 }
00376